1. Field of the Invention
The present invention generally relates to providing test capabilities to an electronic component. More particularly, the invention relates to providing JTAG test capabilities to an electronic component without the use of standard JTAG input/output pins. Still more particularly, the invention relates to an SMBus-to-JTAG emulator to permit a host test system to communicate with the JTAG test port on an electronics assembly using the SMBus.
2. Background Information
It is desirable to test a piece of electronics equipment before it enters the stream of commerce. In the computer arts, the entire computer system is tested as well as various sub-systems contained therein such as add-in cards, displays, and the like. Generally, testing may include verifying the interconnection between components as well as verifying the functionality of various components and sub-subsystems.
More recently, the Institute of Electrical and Electronics Engineering has promulgated an industry test standard designated as IEEE Std 1149.1. This standard, also referred to as the Joint Test Action Group (“JTAG”), is a common protocol and boundary-scan architecture intended to be incorporated into application specific integrated circuits (“ASIC”), add-in cards and the like. In accordance with the JTAG test standard, an add-in card must include certain logic to enable the testing protocols. The JTAG standard also requires a minimum of four signal lines, and an optional fifth signal line, for its implementation. The five signal lines include a serial data input line, a serial data out line, a clock signal, a mode signal and an optional reset signal. Thus, a JTAG-compatible add-in card must dedicate four or five pins on its connector for JTAG testing.
It is generally desirable to have fewer, rather than more, pins on a card connector. Larger connectors occupy more space that can be at a premium in a computer system, particularly in notebook computers. Further, each pin on a connector is susceptible to breaking or otherwise malfunctioning. Thus, fewer pins generally results in a lower probability of connector failure. Accordingly, it would be desirable to provide the benefit of JTAG testing to an add-in card without the increase in pin count that is necessitated by JTAG's implementation.